今日第三天算是整個行程的主軸~月光島之旅~,乘著快艇沿路停靠拖曳傘與潛水的地點後,最後到達了島上,有之前泛舟與浮淺的經驗後,這次相機防水套又派上用場了,也算是本團在水中遊戲中拍最多照片的吧,不過防水套的水滴沒擦掉讓幾張照片多了小水滴,有點美中不足...^^...這個島還真是陽春,香蕉船只繞了小小的一圈,沙灘排球的球場凹凸不平又一堆石頭,至於浮潛ㄋ~~服務生將掛在牆上的蛙鏡交給你後讓你自己由沙灘走去浮淺(大家都被石頭割了好幾下),怎麼沒有像台灣本島還用船到海中央放下海賞魚,而且每個蛙鏡還會進水,我的蛙鏡與塑膠鏡面居然測試的時候就分家了,浮淺的途中還有許多海膽,被刺到可是會哭爸叫母的哦,真是給他拍拍手,午餐的海鮮大餐每桌都是剩下螃蟹與蝦子等海鮮,真懷疑我們是來吃合菜不是吃海鮮大餐的,下午做精油spa與加價600B咖啡去角質流程,晚上到船上釣小管,第一次玩還蠻新鮮的,不過位置剛好在排氣管旁邊以及燈光的邊源處,沒釣到小管所幸就幫大家拍拍照嘍,還偷偷跑到樓上看人妖表演,不過最後被人家的保安人員發現給請出場,接下來的燒烤宵夜算是本團彼此熟悉的開始,當三杯黃湯下肚後,大家比較放的開,咱們的公關組也開始運作了,外加當地導遊的推波助瀾,划拳灌酒都出現了,大約一小時的夜遊暹邏灣後,12名的年輕團員們到PUB續攤,當地導遊手腕算是蠻強的,替我們爭取到了舞台前的座位,在熱歌競舞狀況下結束了今晚,順帶一提的是男生廁所內有按摩小弟在小解之際幫人按摩與敷熱毛巾,不過小費20元是不能少的嘍~
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分享至痞客邦部落格
分享連結
常見的半導體材料有矽、鍺、砷化鎵等
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晶片測試
晶片處理高度有序化的本質增加了對不同處理步驟之間度量方法的需求。晶片測試度量裝置被用於檢驗晶片仍然完好且沒有被前面的處理步驟損壞。如果If the number of dies—the 積體電路s that will eventually become chips—當一塊晶片測量失敗次數超過一個預先設定的閾值時，晶片將被廢棄而非繼續後續的處理製程。
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晶片測試
晶片處理高度有序化的本質增加了對不同處理步驟之間度量方法的需求。晶片測試度量裝置被用於檢驗晶片仍然完好且沒有被前面的處理步驟損壞。如果If the number of dies—the 積體電路s that will eventually become chips—當一塊晶片測量失敗次數超過一個預先設定的閾值時，晶片將被廢棄而非繼續後續的處理製程。
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步驟列表
晶片處理
濕洗
平版照相術
光刻Litho
離子移植IMP
蝕刻（干法蝕刻、濕法蝕刻、電漿蝕刻）
熱處理
快速熱退火Annel
熔爐退火
熱氧化
化學氣相沉積 (CVD)
物理氣相沉積 (PVD)
分子束磊晶 (MBE)
電化學沉積 (ECD)，見電鍍
化學機械平坦化 (CMP)
IC Assembly and Testing 封裝測試
Wafer Testing 晶片測試
Visual Inspection外觀檢測
Wafer Probing電性測試
FrontEnd 封裝前段
Wafer BackGrinding 晶背研磨
Wafer Mount晶圓附膜
Wafer Sawing晶圓切割
Die attachment上片覆晶
Wire bonding焊線
BackEnd 封裝後段
Molding模壓
Post Mold Cure後固化
De-Junk 去節
Plating 電鍍
Marking 列印
Trimform 成形
Lead Scan 檢腳
Final Test 終測
Electrical Test電性測試
Visual Inspection光學測試
Baking 烘烤
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有害材料標誌
許多有毒材料在製造過程中被使用。這些包括：
有毒元素摻雜物比如砷、硼、銻和磷
有毒化合物比如砷化三氫、磷化氫和矽烷
易反應液體、例如過氧化氫、發煙硝酸、硫酸以及氫氟酸
工人直接暴露在這些有毒物質下是致命的。通常IC製造業高度自動化能幫助降低暴露於這一類物品的風險。
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Device yield
Device yield or die yield is the number of working chips or dies on a wafer, given in percentage since the number of chips on a wafer (Die per wafer, DPW) can vary depending on the chips' size and the wafer's diameter. Yield degradation is a reduction in yield, which historically was mainly caused by dust particles, however since the 1990s, yield degradation is mainly caused by process variation, the process itself and by the tools used in chip manufacturing, although dust still remains a problem in many older fabs. Dust particles have an increasing effect on yield as feature sizes are shrunk with newer processes. Automation and the use of mini environments inside of production equipment, FOUPs and SMIFs have enabled a reduction in defects caused by dust particles. Device yield must be kept high to reduce the selling price of the working chips since working chips have to pay for those chips that failed, and to reduce the cost of wafer processing. Yield can also be affected by the design and operation of the fab.
Tight control over contaminants and the production process are necessary to increase yield. Contaminants may be chemical contaminants or be dust particles. "Killer defects" are those caused by dust particles that cause complete failure of the device (such as a transistor). There are also harmless defects. A particle needs to be 1/5 the size of a feature to cause a killer defect. So if a feature is 100 nm across, a particle only needs to be 20 nm across to cause a killer defect. Electrostatic electricity can also affect yield adversely. Chemical contaminants or impurities include heavy metals such as Iron, Copper, Nickel, Zinc, Chromium, Gold, Mercury and Silver, alkali metals such as Sodium, Potassium and Lithium, and elements such as Aluminum, Magnesium, Calcium, Chlorine, Sulfur, Carbon, and Fluorine. It is important for those elements to not remain in contact with the silicon, as they could reduce yield. Chemical mixtures may be used to remove those elements from the silicon; different mixtures are effective against different elements.
Several models are used to estimate yield. Those are Murphy's model, Poisson's model, the binomial model, Moore's model and Seeds' model. There is no universal model; a model has to be chosen based on actual yield distribution (the location of defective chips) For example, Murphy's model assumes that yield loss occurs more at the edges of the wafer (non-working chips are concentrated on the edges of the wafer), Poisson's model assumes that defective dies are spread relatively evenly across the wafer, and Seeds's model assumes that defective dies are clustered together.[25]
Smaller dies cost less to produce (since more fit on a wafer, and wafers are processed and priced as a whole), and can help achieve higher yields since smaller dies have a lower chance of having a defect. However, smaller dies require smaller features to achieve the same functions of larger dies or surpass them, and smaller features require reduced process variation and increased purity (reduced contamination) to maintain high yields. Metrology tools are used to inspect the wafers during the production process and predict yield, so wafers predicted to have too many defects may be scrapped to save on processing costs.[26]